1. Field
This disclosure relates generally to integrated circuits and, more specifically, to techniques for detecting open integrated circuit pins.
2. Related Art
One technique for detecting whether input pins of an integrated circuit (IC) are open, i.e., floating, has used an internal pull-up or pull-down resistor (connected to a defined voltage) on each of the input pins. According to this technique, a determination of whether an input pin is open has been made based on a voltage present on the input pin. However, when a pull-up or pull-down resistor is coupled to an input pin and the defined voltage is used for another circuit within the IC, the pull-up or pull-down resistor may create operational problems for the IC. For example, a pull-up or pull-down resistor on an input pin may modify the performance of an internal cell (of the IC) that is coupled to the input pin or adversely affect a voltage level of a desired input signal on the input pin.
U.S. Pat. No. 5,101,154 (hereinafter the '154 patent) is directed to an open bond detection circuit that is used to verify continuity through bonding wires connected between an external pin and a bonding pad of an integrated circuit (IC). The detection circuit of the '154 patent monitors a voltage potential developed across one or more bonding wires (i.e., metal conductors) connected between a bonding pad and an external pin to determine whether one or more of the bonding wires are open. The open bond detection circuit disclosed in the '154 patent is relatively complex, occupies a relatively large die area, and has relatively high current requirements.
With reference to FIG. 1, a circuit 100 is illustrated that employs a pull-up resistor Rpu between an internal voltage VDDi and an input pin of an integrated circuit (IC) 102 according to the prior art. As is shown, an external voltage Vext may be coupled to an input pin ch1 of the IC 102, via a resistive divider (including resistors R1 and R2). A parasitic external capacitance Cext is also shown coupled to the input pin ch1. In the circuit 100, when the input pin ch1 is open, i.e., when the external voltage Vext is not coupled to the input pin via the resistive divider, the external capacitor Cext charges to a level of the internal voltage VDDi through the pull-up resistor Rpu and, as such, a cell voltage Vc input to internal IC cell 104 transitions to the level of the internal voltage VDDi. In this case, control logic (not shown) detects an open on the input pin ch1 when the cell voltage Vc is approximately equal to the internal voltage VDDi. Unfortunately, coupling the input pin ch1 to the internal voltage VDDi via the pull-up resistor Rpu may adversely affect normal operation of the cell 104 and other circuits coupled to the input pin ch1.
With reference to FIG. 2, a circuit 200 is illustrated that employs a pull-down resistor Rpd to a common point (e.g. ground) on an input pin ch1 of an IC 202 according to the prior art. As is shown, an external voltage Vext may be coupled to the input pin ch1 of the IC 202, via a resistive divider (including the resistors R1 and R2). A parasitic external capacitance Cext is also shown coupled to the input pin ch1. In the circuit 200, when the input pin ch1 is open, i.e., when the external voltage Vext is not coupled to the input pin ch1 via the resistive divider, the external capacitor Cext discharges through the pull-down resistor Rpd and, as such, a cell voltage Vc input to internal IC cell 204 transitions to the value of the common point, e.g., zero volts. In this case, control logic (not shown) detects an open on the input pin ch1 when the cell voltage Vc is approximately equal to the level of the common point. Unfortunately, coupling the input pin ch1 to the common point via the pull-down resistor may adversely affect normal operation of the cell 204 and other circuits coupled to the input pin ch1.
What is needed is a technique for determining whether a pin of an integrated circuit is open that is relatively straight forward to implement and does not adversely affect operation of other external or internal circuits that are coupled to the pin during normal operation of the integrated circuit.